RAM Latency Calculator (CAS Latency to Nanoseconds)

Background.

Memory timings are printed in clock cycles, and clock cycles are not a unit of time until you know how fast the clock runs. That single fact is why a DDR5-6000 CL30 kit and a DDR4-3200 CL16 kit have identical latency despite one advertising a number nearly twice as large as the other, and why the forum reflex that 'lower CL is faster' is wrong roughly as often as it is right. This calculator does the conversion: give it a data rate and a timing string, and it returns the nanoseconds those timings actually cost.

The arithmetic is short. Double data rate means two transfers per clock, so a kit rated 3200 MT/s runs a 1600 MHz clock and one clock period — tCK — is 2000 ÷ 3200 = 0.625 nanoseconds. CAS latency is a count of those periods, so CL22 costs 22 × 0.625 = 13.75 ns. That is not a derivation this page invented: a DDR4 component datasheet for the 3200 MT/s grade lists 0.625 ns cycle time at CL 22, a maximum clock of 1600 MHz, and a tAA of 13.75 ns in the same table. The calculator reproduces the datasheet exactly, which is the point of checking it.

CAS latency alone is also the most optimistic number anyone quotes, because it only applies when the row you want is already open. This page therefore reports three latencies rather than one. A read into an idle bank has to activate the row first and costs tRCD + CL. A read into a bank where a different row is open has to close that row first and costs tRP + tRCD + CL. For a typical DDR4-3200 22-22-22 kit those are 13.75 ns, 27.5 ns and 41.25 ns — a three-fold spread, and which one you get depends on the access pattern rather than on the kit. It also reports tRC, the row cycle time, which is tRAS + tRP and sets how quickly a single bank can be reopened.

Bandwidth is reported alongside, because latency and bandwidth are the two halves of the trade every memory upgrade makes and they move in opposite directions. A 64-bit memory channel moves eight bytes per transfer, so peak bandwidth in decimal GB/s is simply the data rate times eight divided by a thousand: 25.6 GB/s for DDR4-3200, 19.2 GB/s for DDR4-2400 — both of which appear verbatim in the module datasheet cited below. Raising the data rate raises bandwidth linearly and lowers tCK, which is why faster kits usually get away with bigger CL numbers and still come out level or ahead.

Two honest limits. This page computes device-level timings; it does not predict the load-to-use latency a benchmark reports, which additionally includes the memory controller, the interconnect and cache-miss handling, none of which can be derived from a timing string. And it does not tell you whether a given CL is achievable at a given data rate on your hardware — that depends on the DRAM die, the memory controller, the board topology and the voltage. It converts timings into time. Everything else on the page is sourced to a component or module datasheet and named as such.

What is ram latency calculator?

RAM latency is the delay between a memory controller asking a DRAM device for data and that data appearing on the bus. DRAM datasheets specify it in clock cycles, not in time, because the device is synchronous: every internal step takes a whole number of clock periods. The four numbers usually printed on a memory kit are CL (CAS latency, the delay from a read command to the first data when the target row is already open), tRCD (the delay from activating a row to being allowed to issue the read), tRP (the time to close an open row again) and tRAS (the minimum a row must remain open once activated). To turn any of them into nanoseconds you need the clock period, tCK. Because DDR memory transfers on both edges of the clock, the clock frequency is half the advertised transfer rate: a DDR4-3200 kit clocks at 1600 MHz, giving tCK = 0.625 ns. Multiply a cycle count by tCK and you have the time. The headline figure — CL × tCK — is called tAA in JEDEC-style datasheets and 'true latency' in enthusiast usage. Separately, the same data rate fixes the bus's peak throughput: a JEDEC memory channel is 64 data bits wide, so it moves 8 bytes per transfer and its peak bandwidth in decimal GB/s is the data rate times 8 divided by 1000. Latency and bandwidth are independent axes, and a kit can be better on one and worse on the other.

How to use this calculator.

1. 01Enter the data rate. Use the number from the kit's name — 3200 for DDR4-3200, 6000 for DDR5-6000. It is transfers per second, not the clock frequency, and entering the clock instead will halve every latency on the page.
2. 02Enter the timing string in order: CL, tRCD, tRP, tRAS. Most kits print the first three on the label as something like 22-22-22 or 30-38-38; tRAS is the fourth number and appears on the spec sheet or in your BIOS.
3. 03Set the channel count to however many channels your board actually populates — two on a normal desktop, more on a workstation. Channels change bandwidth only, never latency.
4. 04Read the true latency first. That is the number to compare across kits, and it is the only fair way to compare a CL16 DDR4 kit against a CL30 DDR5 one.
5. 05Then read the row-miss and row-conflict figures. If your workload streams through memory it will spend most of its time near the row-miss number, not the CL number, so a kit that wins on CL can still lose on the latency that matters.
6. 06Compare bandwidth last. If you are choosing between a faster kit with looser timings and a slower kit with tighter ones, and their true latencies come out close, the faster kit wins on bandwidth for free.

The formula.

Start with the clock. DDR stands for double data rate: the device transfers on the rising and the falling edge of the clock, so a part advertised at 3200 MT/s is clocked at 1600 MHz. A DDR4 component datasheet makes this explicit by listing a maximum clock of 1600 MHz for its 3200 MT/s speed grade. Turning that into a period, tCK = 1000 ÷ 1600 = 0.625 ns, which is the same as the shortcut used throughout this page: tCK = 2000 ÷ data rate.

Every timing number is then just a count of those periods. CL22 at 0.625 ns per cycle is 13.75 ns, and that figure appears in the datasheet's own key-timing table as tAA = 13.75 ns for a 22-22-22 part. tRCD and tRP are quoted at the same 13.75 ns there, because that particular grade uses equal values for all three — which is exactly why a timing string reads 22-22-22.

The three latency outputs correspond to the three states a bank can be in when a read arrives. If the wanted row is already open — a row hit — the only cost is CL, so tAA is the answer. If the bank is idle, the controller must issue an ACTIVATE and wait tRCD before the read, so the cost is (tRCD + CL) × tCK. If a different row is open in that bank, it must first be closed with a PRECHARGE costing tRP, then activated, then read: (tRP + tRCD + CL) × tCK. Row hits are cheap and row conflicts are three times as expensive, and no single number describes both.

tRC, the row cycle time, is tRAS + tRP. tRAS is the minimum a row must stay open after activation and tRP is the time to close it, so their sum is the shortest possible interval between two activates on the same bank. It is the reason a workload that keeps hammering one bank cannot go faster than about 46 ns per row on a typical DDR4-3200 kit, no matter what the data rate is.

Bandwidth is independent of all of that. A JEDEC memory channel is 64 data bits — eight bytes — wide, so peak throughput is transfers per second times eight bytes. At 3200 MT/s that is 25,600 MB/s, which vendors write as 25.6 GB/s using decimal gigabytes; the same module datasheet prints 21.3 GB/s at 2666 MT/s and 19.2 GB/s at 2400 MT/s, and both match the arithmetic. Multiply by the channel count for the system total. This is a theoretical ceiling: refresh cycles, bank conflicts and read-to-write bus turnaround all consume slots, so measured throughput is always lower.

One consequence worth stating plainly. Because tCK shrinks as the data rate rises, a larger CL at a higher speed can cost the same time as a smaller CL at a lower one. DDR5-6000 CL30 is 30 × (2000 ÷ 6000) = 10.00 ns. DDR4-3200 CL16 is 16 × 0.625 = 10.00 ns. Identical latency — but the DDR5 kit moves 48 GB/s per channel against the DDR4 kit's 25.6 GB/s. Comparing CL numbers across generations without doing this conversion is the single most common mistake in memory shopping.

A worked example.

Frequently asked questions.

References& sources.

1. [1]Alliance Memory. AS4C2G16D4 32Gb (2G x 16) DDR4 SDRAM datasheet, Rev 1.0, September 2024. Source of the DDR4-3200 figures reproduced on this page: the feature list's cycle time '0.625ns @ CL = 22 (DDR4-3200)'; Table 1 Key Timing Parameters giving speed grade -62 at 3200 MT/s with target CL-nRCD-nRP 22-22-22 and tAA, tRCD and tRP all 13.75 ns; and Table 2 Ordering Information giving a maximum clock of 1600 MHz for that 3200 MT/s part.
2. [2]Micron Technology. MTA8ATF1G64HZ 8GB DDR4 SDRAM SODIMM datasheet. Source of the bandwidth relation used here: the part table lists the 1 Gig x 64 module at 25.6 GB/s and 0.62ns/3200 MT/s with 22-22-22 timings, 21.3 GB/s at 2666 MT/s and 19.2 GB/s at 2400 MT/s — all three consistent with 8 bytes per transfer on a 64-bit channel and decimal GB/s. Also the source of the cycle times 0.62 ns at CL 22, 0.75 ns at CL 19 and 0.83 ns at CL 17.
3. [3]Micron Technology. 128GB DDR5 RDIMM product brief. Source of the published DDR5 speed grades quoted on this page — 5600 MT/s, 6400 MT/s, 7200 MT/s and 8000 MT/s — which set the upper bound accepted by the data-rate input.
4. [4]Samsung Semiconductor. DRAM UDIMM product page. Source of the generational speed context used in the FAQ: DDR4 UDIMM 'Up to 3,200 Mbps' and DDR5 UDIMM 'Up to 5,600 Mbps', which is the JEDEC-grade ceiling that XMP and EXPO kits deliberately exceed.