Transistor Biasing Calculator — BJT Q Point, V_CE and β Stability

Background.

A bipolar transistor does nothing useful until it is biased. Bias is the DC operating point — the collector current and collector-emitter voltage present with no signal applied — and the whole job of the resistor network round a transistor is to put that point somewhere sensible and keep it there. This page takes the three bias networks that account for almost every discrete BJT stage ever built and returns the full operating point for each: I_CQ, V_CEQ, every node voltage, the base current, the load-line endpoint, and a stability figure that tells you how much of the answer depends on the transistor rather than on your resistors.

The problem bias solves is that β is not a number. A 2N3904 is specified with a DC current gain anywhere from 100 to 300 at 10 mA — a three-to-one spread across parts from the same reel, before temperature moves it further. Any bias scheme whose operating point is proportional to β therefore produces a different circuit every time you build it. The fix, in all three networks here, is negative feedback: put a resistor in the emitter, and any rise in current lifts the emitter voltage, which eats into V_BE and pushes the current back down. The stability output on this page measures exactly how well that works, by recomputing the Q point with β halved and reporting how far I_C moved.

Voltage-divider bias is the default choice and the default mode here. Two resistors set a fixed base voltage from a single supply, the emitter resistor sets the current, and provided the divider is stiff enough to ignore the base current the transistor's own gain barely enters the answer. Two-supply emitter bias does the same job with a negative rail instead of a divider and is the most stable of the three. Collector-feedback bias uses one resistor from collector to base; it is cheap and self-correcting but only modestly stable, which the numbers on this page show plainly — the worked collector-feedback example moves 13 % when β halves, against 0.5 % for the divider circuit.

Every equation implemented here is taken verbatim from Chapter 5 of James Fiore's *Semiconductor Devices: Theory and Application*, and all three of that chapter's published worked examples are pinned by tests. Those equations carry the standard textbook approximation that I_C equals I_E, which is what makes the arithmetic tractable by hand; the exact β model gives a collector current lower by the factor β/(β+1), about half a percent at β = 200. That limit, along with the fixed V_BE, the ignored Early effect and the absence of any temperature model, is stated beside the result rather than buried in an FAQ, because it changes how the number should be read. Use the output as a design centre and check it against the datasheet and the tolerances of the parts actually in front of you.

What is transistor biasing calculator?

Biasing is the act of setting a transistor's DC operating point so that an AC signal has room to swing in both directions without the device turning off or bottoming out. The operating point, universally called the Q point, is the pair (I_CQ, V_CEQ). Draw the DC load line on the transistor's output curves — a straight line from V_CE = V_CC at zero current down to I_C = V_CC/(R_C + R_E) at zero volts — and the Q point is where the bias network puts you along that line. Sit too near the bottom and the stage saturates on positive-going input; too near the top and it cuts off. Roughly halfway gives the largest symmetrical swing, which is why comparing I_CQ with the saturation-current output on this page is a fast sanity check on any design. The three networks offered here differ only in how they establish base current. Voltage-divider bias holds the base at a fixed fraction of V_CC using two resistors, so the emitter sits one V_BE below that and R_E fixes the current. Two-supply emitter bias grounds the base through R_B and returns R_E to a negative rail, so the emitter is held near −0.7 V and the current is (|V_EE| − V_BE)/R_E. Collector-feedback bias feeds the base from the collector itself, so any increase in collector current lowers the collector voltage and starves the base — a self-correcting loop, but a weaker one than an emitter resistor provides.

How to use this calculator.

1. 01Pick the bias network your circuit actually uses. The three have different equations and there is no single formula that covers them all.
2. 02Enter the supply voltage or voltages. For two-supply emitter bias, enter |V_EE| as a positive magnitude — the calculator handles the sign.
3. 03Enter the resistor values in kilohms. Fields the selected network does not use are ignored, so a leftover value in R₁ will not affect an emitter-bias calculation.
4. 04Enter β from the datasheet. Use the typical figure first, then try the minimum and maximum: if the Q point moves a lot between them, the bias network is the problem, not the transistor.
5. 05Read I_CQ and V_CEQ. Check that V_CEQ clears the V_CE(sat) threshold and that I_CQ is somewhere near half the load-line saturation current.
6. 06Read the β-shift figure. Under about 5 % means the resistors are in charge; above 20 % means the transistor is, and the built circuit will not match the calculation part to part.
7. 07In voltage-divider mode, check the divider-stiffness sentence. If the divider current is not at least ten times the base current, lower R₁ and R₂ before trusting the base voltage.

The formula.

Start with the base divider. Thévenin's theorem replaces R₁ and R₂ with a single source V_TH = V_CC·R₂/(R₁+R₂) behind a resistance R_TH = R₁R₂/(R₁+R₂). For the worked example — 15 V, R₁ = 10 kΩ, R₂ = 4.7 kΩ — that is V_TH = 4.7959 V behind R_TH = 3.1973 kΩ.

Walk the base-emitter loop. The Thévenin source has to supply the V_BE drop plus whatever appears across R_E, and the base current flowing in R_TH costs a little more. Collecting terms gives Fiore's Equation 5.8, I_C = (V_TH − V_BE)/(R_E + R_TH/β). With β = 200 the R_TH/β term is only 15.99 Ω against 3300 Ω of emitter resistance, so it barely matters — which is precisely the point of the design. The result is I_C = 4.0959 V / 3315.99 Ω = 1.2352 mA.

The node voltages follow. V_E = I_C·R_E = 4.0762 V, and the base sits one diode drop above it at V_B = 4.7762 V. The collector is V_C = V_CC − I_C·R_C = 10.1827 V, so V_CE = V_C − V_E = 6.1065 V, which is the same thing Equation 5.9 gives directly as V_CC − I_C(R_C + R_E). Base current is I_C/β = 6.176 µA.

Rounding happens once, at the end. Every intermediate value is carried at full precision and only the displayed outputs are rounded to ten decimal places, and both classification bands read the unrounded numbers. That is worth spelling out because the source textbook does the opposite: Fiore prints V_TH as 4.8 V and R_TH as 3.2 kΩ, then computes from those two-significant-figure values and gets 1.236 mA. Carrying full precision gives 1.2352 mA. The two agree to three significant figures — 1.24 mA — and the difference is entirely rounding stage, not disagreement about the physics.

The stability figure comes from running the same equation twice. Halve β to 100 and the divider example gives 1.2293 mA, a shift of 0.48 %, which matches the source's own statement that this circuit moves less than 1 % when β halves. Run the collector-feedback example the same way — 15 V, R_C = 10 kΩ, R_B = 180 kΩ — and I_C falls from 1.2119 mA at β = 100 to 1.0515 mA at β = 50, a 13.2 % shift. The published values for that example are 1.21 mA and 1.05 mA. That is the difference between the two topologies, in one number.

What the model leaves out: V_BE is fixed rather than logarithmic in current and moves about −2 mV/°C in a real junction; the Early effect is ignored, so I_C does not depend on V_CE; leakage is ignored; and I_C is taken as equal to I_E, which overstates I_C by the factor (β+1)/β — 0.5 % at β = 200, 2 % at β = 50. None of these change the shape of the answer, and all of them are smaller than a 5 % resistor tolerance, but they are why a measured circuit never lands exactly on the calculated figure.

A worked example.

Frequently asked questions.

References& sources.

1. [1]James M. Fiore, 'Semiconductor Devices: Theory and Application', Chapter 5 'BJT Biasing', Engineering LibreTexts (open-access textbook). Primary source for every equation implemented: Eq 5.1 I_C = (|V_EE| − V_BE)/(R_E + R_B/β) and Eq 5.3 V_CE = V_CC + |V_EE| − I_C(R_C + R_E) for two-supply emitter bias; Eq 5.6 I_C(sat) = V_CC/(R_C + R_E) and Eq 5.7 V_CE(cutoff) = V_CC for the load line; Eq 5.8 I_C = (V_TH − V_BE)/(R_E + R_TH/β) and Eq 5.9 V_CE = V_CC − I_C(R_C + R_E) for voltage-divider bias; Eq 5.10 I_C = (V_CC − V_BE)/(R_C + R_B/β) and Eq 5.11 for collector feedback. Also the source of the three worked examples pinned by this page's tests — Example 5.4.1 (1.236 mA, 6.1 V, V_B ≈ 4.78 V), Example 5.1 (3.38 mA, 9.72 V) and Example 5.5.1 (1.21 mA, 2.9 V, falling to 1.05 mA and 4.5 V when β halves) — and of the stated V_BE = 0.7 V. Retrieved 2026-07-29.
2. [2]Analog Devices Wiki, 'Chapter 9: Single Transistor Amplifier Stages' (ADI university program teaching text). Consulted as an independent authority, not used for the derivation. Gives V_B = R_B2/(R_B1+R_B2)·V_CC and V_E = V_B − V_BE, agreeing with this page's node relations, and supplies the divider-stiffness design rule used in the verdict: 'Save power by allowing only 10 % of I_E in R_B', i.e. V_CC/(R_B1+R_B2) ≈ 0.1·I_E. Applied to the worked example the unloaded base voltage is 4.796 V against the loaded 4.776 V computed here, and the divider-to-base current ratio is 165:1 — comfortably above the rule. Retrieved 2026-07-29.
3. [3]onsemi (Semiconductor Components Industries), '2N3904 General Purpose Transistors' datasheet, Rev. 1 (2N3904/D). Source of the editable V_CE(sat) default: collector-emitter saturation voltage 0.2 V maximum at I_C = 10 mA with I_B = 1.0 mA, and 0.3 V maximum at I_C = 50 mA with I_B = 5.0 mA. Also the source of the β range quoted throughout this page — h_FE is specified as a min/max band rather than a single value, 100 to 300 at I_C = 10 mA. PDF datasheet. Retrieved 2026-07-29.
4. [4]James M. Fiore, 'Semiconductor Devices: Theory and Application', §5.6 'Summary', Engineering LibreTexts. Source of the comparative stability ranking stated on this page: two-supply emitter bias offers 'very high Q point stability', voltage divider bias 'similar stability performance', and feedback bias configurations 'only modest enhancements in stability'. This page's β-shift output makes that ranking numeric — 0.48 %, 1.82 % and 13.2 % for the three worked examples respectively. Retrieved 2026-07-29.